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2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 141
PIC18CXX8
15.3
SPI Mode
The SPI mode allows 8 bits of data to be synchronously
transmitted and received, simultaneously. All four
modes of SPI are supported. To accomplish communi-
cation, typically three pins are used:
Serial Data Out (SDO) - RC5/SDO
Serial Data In (SDI) - RC4/SDI/SDA
Serial Clock (SCK) - RC3/SCK/SCL/LVOIN
Additionally, a fourth pin may be used when in any
Slave mode of operation:
Slave Select (SS) - RA5/SS/AN4
15.3.1
OPERATION
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits SSPCON1<5:0> and SSPSTAT<7:6>.
These control bits allow the following to be specified:
Master mode (SCK is the clock output)
Slave mode (SCK is the clock input)
Clock polarity (Idle state of SCK)
Data input sample phase (middle or end of data
output time)
Clock edge (output data on rising/falling edge of
SCK)
Clock rate (Master mode only)
Slave Select mode (Slave mode only)
Figure 15-1 shows the block diagram of the MSSP
module, when in SPI mode.
FIGURE 15-1: MSSP BLOCK DIAGRAM
(SPI MODE)
The MSSP consists of a transmit/receive Shift Register
(SSPSR) and a buffer register (SSPBUF). The SSPSR
shifts the data in and out of the device, MSb first. The
SSPBUF holds the data that was written to the SSPSR,
until the received data is ready. Once the 8 bits of data
have been received, that byte is moved to the SSPBUF
register. Then the buffer full detect bit, BF (SSPSTAT
register), and the interrupt flag bit, SSPIF (PIR regis-
ters), are set. This double buffering of the received data
(SSPBUF) allows the next byte to start reception before
reading the data that was just received. Any write to the
SSPBUF register during transmission/reception of data
will be ignored, and the write collision detect bit, WCOL
(SSPCON1 register), will be set. User software must
clear the WCOL bit so that it can be determined if the
following write(s) to the SSPBUF register completed
successfully.
(
)
Read
Write
Internal
Data Bus
SSPSR reg
SSPM3:SSPM0
bit0
Shift
Clock
SS Control
Enable
Edge
Select
Clock Select
TMR2 Output
TOSC
Prescaler
4, 16, 64
2
Edge
Select
2
4
Data to TX/RX in SSPSR
TRIS bit
2
SMP:CKE
SDI
SDO
SS
SCK
Note:
I/O pins have diode protection to VDD and
VSS.
SSPBUF reg
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